When two or more layers are deposited and the upper layer is to be etched during the fabrication of a semiconductor device, an end point detection (EPD) system is generally used in the etching process. The EPD system sets an etch stop point (e.g., the point at which the lower layer is exposed when etching the upper layer).
However, it is difficult to determine the etch stop point using the lower layer by the current EPD system for hole etching process, (which is used for forming contact holes or via holes), because the area exposed by via holes is small, (e.g., under 5% of the whole wafer area). Therefore, conventional time etching is used instead.
FIGS. 1aand 1b are sectional views illustrating a conventional hole etching process for a semiconductor device. As shown in FIG. 1a, an interlayer insulating layer 1, in which holes will be formed, is first formed. A nitride layer 2, which will be used as a hard mask, is formed on the interlayer insulating layer 1. A photoresist pattern 3 is formed on the nitride layer 2. The nitride layer 2 is etched using the photoresist pattern 3 as a mask to form a nitride layer pattern 4 as shown in FIG. 1b. 
Subsequently, the interlayer insulating layer 1 is time-etched using the nitride pattern 4 as a mask to form holes 5. The etching time, which is set for the hole formation, is determined by considering the etch rate of the interlayer insulating layer 1.
However, the time-etching is based on a premise that the conditions or state in a chamber are always the same. Therefore, there is a problem that the interlayer insulating layer cannot be etched to a desired extent if there is a change in the etch rate of the etching chemical or if there is a change in the thickness of the interlayer insulating layer after the CMP.
Prior art references dealing with the subject matter of the etch stop layer include the following U.S. patents.
U.S. Pat. No. 6,383,943 describes a method of resolving a problem of discontinuous deposition of an adhesive layer at the bottom of via holes due to a notch of the silicon nitride etch stopper. U.S. Pat. No. 6,040,619 describes a formation method for a tungsten Damascene interconnect of a device using silicon nitride having a large amount of silicon as an etch stopper. U.S. Pat. No. 6,063,711 describes a method of forming a thin etch stop layer including oxynitride having large etching selectivity to oxide layer and preventing the etch stop layer from cracking. U.S. Pat. No. 6,245,663 describes a method of forming a thin etch stop layer by forming a dielectric etch stop layer after a metal CMP process instead of before the metal CMP process to prevent the etch stop layer being trimmed during the CMP. U.S. Pat. No. 5,612,254 describes a method of forming an interconnection inside the prepatterned channel in a semiconductor device.
In the drawings, the thickness of layers and regions are exaggerated for clarity.